1. Technical Field
The present invention relates to a NAND type flash memory array and a method for operating the same, and more particularly to a NAND type flash memory array with a cell structure which is doped with shallow junction on fully depleted silicon on insulator (FDSOI) and a method for operating the same.
2. Description of Related Art
As the mobile and multi-media industry has been developed recently, a demand for flash memory has been increasing.
Now, an application of flash memory enables one to store and update at any time system BIOS such as networking apparatuses (router, hub and so on), mobile phones and PDAs (personal digital assistants) and flash memory is a highly marketable product as a recording device suitable for large amounts of information, specifically, solid state memory, such as memory card, digital camera, voice/image storage device and portable computer. As multi-media applications have been increasing rapidly, a demand for storage medium with various uses has been increasing suddenly and the application field of flash memory devices continues to grow.
A common flash memory is classified as NOR or NAND type, according to its array organization of unit cells. In a NOR type flash memory, the speed of programming is rapid due to a CHE injection program mechanism, and the random access characteristic is excellent due to the cell array structure. However, it has a relative weak point for integration. On the contrary, in a NAND type flash memory, the speed of programming is slow due to an F-N tunneling mechanism, and the random access characteristic is not good. But the integration capability of the NAND type memory is excellent. So, a NAND type flash memory is economically superior to a NOR type flash memory array. Therefore, a NOR type flash memory can be utilized in a field which requires rapid random access and a NAND type flash memory can be utilized in a recording device suitable for large amounts of information in which the random access time is not as important.
A reduction in memory cell size has been caused by the drive to improve the integration of flash memory. When trying to scale down memory cell size, to prevent short channel effect and other adverse results, research has been proceeding on the flash memory cell on fully depleted silicon on insulator substrates (FDSOI). However, a NAND type flash memory array with FDSOI has difficulty in applying an appropriate body bias to the fully depleted body region and it makes erasing a memory cell difficult.
On programming a conventional NAND type flash memory, to prevent slight program disturbance of the other cells near the objective cell to be programmed, high voltage VPASS has been applied not to word lines including the objective cell but to all the other word lines. However, there is still slight program disturbance, and it is a factor which limits the number of programs in a NAND type flash memory array.
A conventional NAND type flash memory array has a structure in which unit memory cells are arranged in series as shown in FIG. 1 and the number of unit memory cells is from 8 to 32. To operate the memory, voltages are applied to each line as shown in TABLE 1.
TABLE 1EraseProgramReadPGM W/L 015~200Pass W/L 010 4.5SSLFVcc4.5GSLF04.5CSLF00SEL B/LF01.2UNS B/LFVcc<0.8Bulk2100
Especially, on programming cell A, high voltage of from 15 to 20V is applied to word line W/L1, to which the gate of cell A is connected electrically, and this makes the other cells (such as cell C), which are not to be programmed but hold the word line W/L1 in common, programmed due to the high voltage of the same word line. To prevent this in a conventional NAND array, a self-boosting method is adopted wherein a voltage of 0V (ground) is applied to the bit line B/L0, which an objective cell to be programmed is connected electrically to, and voltage VCC is applied to the other bit lines (such as B/L1), which the other cells not to be programmed are connected electrically to, as shown in TABLE 1. This makes the B/L0 selective transistor turned on, transmitted voltage 0V (ground) to the channel of the objective cell to be written, and accomplishes the program operation, and this makes the other selective transistors of unselected B/Ls (such as B/L1) turned off, thereby floating all the memory cells which are connected to the unselected B/Ls (such as B/L1). Then, the channel potential under the gate of the floated cells (such as C) is determined by the voltages applied to word lines and the capacitors between the control gate and the body. So, for example, the degree of programming of cell C is determined by the difference between the voltage applied to W/L1 and the determined channel potential.
To decrease the degree of programming of cell C, its channel potential should be increased. And to increase the channel potential, a high voltage should be applied to the other word lines, which are not connected electrically to the objective cell. This high voltage is the voltage VPASS, and is around 10V in a conventional type NAND array as shown in TABLE 1. When the voltage VPASS is too low, the self-boosting is ineffective and cell C is interfered. When the voltage VPASS is too high, cell B is interfered. This interference does harm to the reliability of the memory cell, and it is a factor which limits the number of programs.
When trying to scale down a memory cell on a bulk substrate, to prevent degradation, researchers have studied methods to improve characteristics of the transistor of each cell by manufacturing memory cells on FDSOI.
However, in a conventional NAND type flash memory array with an SOI structure, it is impossible to erase a flash memory as in TABLE 1, because a bulk bias is not applied. If the erasing operation is attempted by applying a body voltage to a bulk under the insulator, the very high voltage, higher than the usual voltage, should be applied to it, due to a low efficiency of the body voltage transmitted to the channel by the small capacitance of the insulator.
When manufacturing a memory cell with a usual bulk structure, in which the silicon region on insulator is bulky, there is no problem in the erasing operation. However, characteristics of the reading and programming operation become just the same as an array which is manufactured with a bulk structure, and so there is no usefulness for the SOI substrate.